| Episode |
Date |
Text |
Subject |
Teacher |
| 1 |
12 Apr 2005 |
Appel 1, p.16, 2.1–2.2, pp.39–41,
3.1, pp.72–75,92–95, Fig. 4.7 |
Compiler architecture. Preprocessing, lexical and
syntactical analyses. Abstract syntax trees. |
AW |
| 2 |
12 Apr 2005 |
Appel 5.1,5.3-5.4, pp.125–133,
pp.150–173 |
Symbol tables, type analysis, activation
frames, register and calling conventions of TMS320C6xxx. |
AW |
| 3 |
15 Apr 2005 |
this paper |
Introduction of the DSP hardware platform |
OW |
| 4 |
19 Apr 2005 |
Appel pp. 150—173 (perhaps omitting
152,154—157) and Appel pp. 191-202 |
Intermediate representation and instruction selection |
AW |
| 5 | 19 Apr 2005 | Appel pp.218—223,225—229,
235—248. Optionally section 11.5. Skim section 2.4.1 of
Programmer's Guide (spru 198). |
Register allocation, liveness analysis |
AW |
| 6 |
4 May 2005 |
Appel pp.383—393 (skim 17.1), p.410,
18.1—18.3 (perhaps omit pp. 424—425), 18.5. |
Dataflow analysis: reaching definitions,
constant propagation, copy propagation, available expressions,
reaching expressions, common subexpression elimination, dead code
elimination. Loop optimizations: dominators & loops, loop
invariants, hoisting, induction variables, strength reduction,
loop unrolling. |
AW |
| 7 |
4 May 2005 |
Appel p. 474—488, 503—504, 21.4—21.5 |
Software Pipelining and scheduling without
and with resource bounds. Software Pipelining and scheduling in
cl6x. Memory hierarchy: alignement in the instruction
cache, loop interchange & blocking. |
AW |